1. Field of the Invention
This invention relates to a process for forming a semiconductor device and, more particularly, to a process for forming multilayer metal systems and multilayer interconnections.
2. Description of the Related Art
Multilayer interconnections are an important feature of large scale integrated circuits. It is common in large scale integrated circuits to make connections between devices or between devices and external contacts through a series of wiring lines formed on different levels of a device. Thick layers of insulating material physically and electrically separate wiring lines on different levels of the device. Connections between wiring lines on different levels are formed through relatively narrow openings formed in the insulating layer that separates the wiring lines on different levels. Multilayer wiring structures are unavoidable in current integrated circuit designs, since it is presently the only way in which the many interconnections necessary to a semiconductor circuit can be made. On the other hand, multilayer wiring structures can be difficult to manufacture, since many careful alignment steps must be performed to successfully complete the wiring structure.
FIG. 1 illustrates a semiconductor device incorporating such a multilayer wiring structure. Wiring line 14, which may include one or more metals, alloys, suicides of metals or polysilicon, is formed on the surface of a substrate 10. The substrate 10 may be a silicon chip having a device formed therein, with the wiring line 14 formed on the surface of the silicon chip or the wiring line can be formed on an insulation layer on the surface of the silicon chip. Insulating layer 12 is deposited on the substrate 10 and over the wiring line 14, and then a via is formed through the insulating layer 12 to expose a portion of the first level wiring line 14. A second level wiring line 16 is then deposited on the insulating layer 12 so as to extend into the via, making contact with the first level wiring line within the via. Another insulating layer is deposited on the surface of the first insulating layer 12 and covering the second level wiring line 16. A via is formed in the second insulating layer 18, and a third level wiring line 19 is formed on the surface of the second insulating layer 18 so as to make contact with the second level wiring line 16 through the via. In this way, electrical connection is established between the first level wiring line 14 and the third level wiring line 19.
The process used to form the structure illustrated in FIG. 1 relies on the use of a series of critical alignment steps, including the positioning of a first level via mask in proper registration with first level wiring line 14. Subsequently, a second level conductive layer is patterned to define second level wiring line 16 so that the wiring line extends through the first level via to make contact with the first level wiring line 14. Another alignment step is required to properly position a second level via mask on the second insulating layer 18 in proper registration with the second level wiring line 16. Each of the masking steps in this process is subject both to errors in mask formation and to errors in mask alignment. Sufficient errors in mask formation can reduce the yield of the semiconductor device, and may require the production of a new mask. Errors in mask alignment can also reduce the yield of the semiconductor device, with a fraction of all wafers being rendered defective at each mask alignment step. It would therefore be desirable to reduce the number of mask alignment steps required in the formation of a semiconductor device, particularly those mask alignments that relate to the formation of non-self aligned structures such as vias. In addition, using fewer masks provides the additional benefit of shorter cycle time, since less time is occupied by the process of aligning masks.